(linke Hälfte passt.) |
(No difference)
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Revision as of 18:53, 14 February 2017
Pin | Side B | Side A | Description |
---|---|---|---|
1 | VCC? | PRSNT1# | Must connect to farthest PRSNT2# pin |
2 | VCC? | +12 V | Main power pins |
3 | VCC? | +12 V | |
4 | ? | Ground | |
5 | ? | TCK | SMBus and JTAG port pins |
6 | PERSTN | TDI | |
7 | ? | TDO | |
8 | ? | TMS | |
9 | ? | +3.3 V | |
10 | ? | +3.3 V | Standby power |
11 | ? | PERST# | Link reactivation; fundamental reset |
Key notch | |||
12 | ? | Ground | Request running clock |
13 | ? | REFCLK+ | Reference clock differential pair |
14 | GND | REFCLK− | Lane 0 transmit data, + and − |
15 | PER_0_P | Ground | |
16 | PER_0_N | HSIp(0) | Lane 0 receive data, + and − |
17 | GND | HSIn(0) | |
18 | GND | Ground | |
19 | PER_1_P | Reserved | Lane 1 transmit data, + and − |
20 | PER_1_N | Ground | |
21 | GND | HSIp(1) | Lane 1 receive data, + and − |
22 | GND | HSIn(1) | |
23 | PER_2_P | Ground | Lane 2 transmit data, + and − |
24 | PER_2_N | Ground | |
25 | GND | HSIp(2) | Lane 2 receive data, + and − |
26 | GND | HSIn(2) | |
27 | PER_3_P | Ground | Lane 3 transmit data, + and − |
28 | PER_3_N | Ground | |
29 | GND | HSIp(3) | Lane 3 receive data, + and − |
30 | GND | HSIn(3) | |
31 | PER_4_P | Ground | |
32 | PER_4_N | Reserved | |
33 | GND | Reserved | Lane 4 transmit data, + and − |
34 | GND | Ground | |
35 | PER_5_P | HSIp(4) | Lane 4 receive data, + and − |
36 | PER_5_N | HSIn(4) | |
37 | GND | Ground | Lane 5 transmit data, + and − |
38 | GND | Ground | |
39 | PER_6_P | HSIp(5) | Lane 5 receive data, + and − |
40 | PER_6_N | HSIn(5) | |
41 | GND | Ground | Lane 6 transmit data, + and − |
42 | GND | Ground | |
43 | PER_7_P | HSIp(6) | Lane 6 receive data, + and − |
44 | PER_7_N | HSIn(6) | |
45 | GND | Ground | Lane 7 transmit data, + and − |
46 | ? | Ground | |
47 | VCC? | HSIp(7) | Lane 7 receive data, + and − |
48 | VCC? | HSIn(7) | |
49 | VCC? | Ground |